Exemplary embodiments relate to a semiconductor device and an operating method thereof and, more particularly, to an operation of verifying a program operation.
The program operation of a semiconductor device includes a program pulse operation that raises the threshold voltage of a memory cell to be programmed by supplying a program pulse to a word line coupled to the memory cell and a verify operation that determines whether the raised threshold voltage has reached a target level. The verify operation is described in detail below.
In a single level cell (hereafter referred to as an SLC) programmed in a single level, a single verify level is used in a verify operation because the SLC have one target level. More specifically, the verify operation of the SLC is performed to determine whether the threshold voltage of the SLC is higher than or lower than a verify voltage by supplying the verify voltage, which has a target level, to a word line coupled to the SLC.
In case of a multi-level cell (hereafter referred to as an MLC) programmed in a plurality levels, a plurality of verify voltages are used in a verify operation because the MLC has a plurality of target levels. Accordingly, the verify operation of MLCs is performed in such a way as to sequentially verify the threshold voltages of the MLCs from an MLC having the lowest target level to an MLC having the highest target level.
For example, if one memory cell is programmed in a first state, a second state higher than the first state, or a third state higher than the second state according to the threshold voltage of the memory cell, a verify operation corresponding to the first state is first performed, and verify operations corresponding to the second and the third states are sequentially performed after the verify operation of the first state. A program operation is repeated until the threshold voltages of memory cells to be programmed reaches respective target levels while changing the potentials of bit lines corresponding to the memory cells in response top the result of the verification.
Particularly, a verify operation includes a precharge operation where a bit line is precharged, an evaluation operation where the state of a memory cell corresponding to the bit line is outputted or incorporated into the potential of the bit line, and a sense operation that determines whether the threshold voltage of the memory cell has reached a target level in response to a changed potential of the bit line. Accordingly, the time taken to perform the verify operation of an MLC is increased because the MLC has a plurality of verify levels. Also leakage may occur as a result of the long verify operation. Consequently, a semiconductor device may have deteriorated reliability.